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COMPUTER ARCHICTURE AND ORGINATION PROCESSING UNIT Fundamental Concepts, Execution of a Complete Instruction, Hardwired Control, Performance Consideration, Microprogrammed Control, Microinstructions, Microprogram Sequencing.

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COMPUTER ARCHICTURE AND ORGINATION 

UNIT 3 PROCESSING UNIT 

SHORT NOTES


COVERED TOPICES:- Fundamental Concepts, Execution of a Complete Instruction, Hardwired Control, Performance Consideration, Microprogrammed Control, Microinstructions, Microprogram Sequencing.

Q.1 Explain Hardwired Control Unit With Diagram?

Hardwired Control Unit is a type of control unit in a computer's central processing unit (CPU) that is implemented using combinational logic circuits. It uses fixed wiring to control the sequence of operations in the CPU's execution cycle. Here's how it works:

Hardwired Control Unit Diagram: [INSERT DIAGRAM HERE]

In a hardwired control unit, the control signals are generated by a network of logic gates based on the instruction opcode. Each instruction opcode is decoded to produce a unique set of control signals that coordinate the execution of the instruction.

Q.2 Explain the functioning of Control Unit in Hardwired implementation?

In a hardwired implementation, the control unit generates control signals using fixed logic circuits. When an instruction is fetched from memory, its opcode is decoded by the control unit to determine the sequence of microoperations required to execute the instruction.

The control unit then generates control signals based on the opcode, which activate the appropriate functional units and data paths in the CPU to perform the required operations. Once the instruction execution is complete, the control unit moves on to the next instruction in the program sequence.

Q.3 Explain Prefetching Microinstruction in Detail?

Prefetching microinstruction is a technique used in microprogrammed control units to improve performance by fetching and decoding microinstructions in advance of their execution. Here's how it works:

When a microinstruction is fetched from memory, the control unit checks if there are any subsequent microinstructions that can be prefetched based on the current instruction's opcode or address. If prefetching is possible, the control unit fetches the next microinstruction(s) and stores them in a prefetch buffer.

When the current microinstruction completes execution, the prefetched microinstructions are already available in the prefetch buffer, reducing the time required to fetch and decode them. This helps to overlap instruction fetch and execution, improving overall system performance.

Q.4 Draw and explain Register Transfer Mechanism for Single Bus Organisation?

Register Transfer Mechanism for Single Bus Organization involves the transfer of data between registers using a single data bus. Here's how it works:

[INSERT DIAGRAM HERE]

In this mechanism, data is transferred between registers using a single data bus and control signals to select the source and destination registers. The control unit generates control signals to activate the appropriate registers and enable data transfer on the bus.

Q.5 Explain the Execution of a Complete Instruction?

The execution of a complete instruction involves several steps, including instruction fetch, instruction decode, operand fetch, execution, and result write-back. Here's a brief overview:

  1. Instruction Fetch: The instruction is fetched from memory and loaded into the instruction register (IR).
  2. Instruction Decode: The opcode of the instruction is decoded to determine the operation to be performed.
  3. Operand Fetch: If the instruction requires operands from memory or registers, they are fetched and loaded into the appropriate registers.
  4. Execution: The CPU executes the instruction by performing the specified operation on the operands.
  5. Result Write-back: The result of the operation is written back to memory or registers, depending on the instruction.

Q.6 Draw the Single bus organization of the data path of the CPU and show the control sequence for the execution of Add (R3), R1 for this organization.

[INSERT DIAGRAM HERE]

In a single bus organization, the CPU data path consists of registers, arithmetic and logic units (ALU), and a single data bus for transferring data between components. Here's how the control sequence for executing the Add (R3), R1 instruction works:

  1. R3 and R1 are loaded into the appropriate registers.
  2. The control unit activates the ALU and selects the Add operation.
  3. The values from registers R3 and R1 are passed to the ALU via the data bus.
  4. The ALU performs the addition operation, and the result is stored back into register R3.

Q.7 Draw the Single bus organization of the data Path of the CPU and show the control sequence for the Execution of MUL(R3), R1 for this organization.

[INSERT DIAGRAM HERE]

Similarly, for the MUL(R3), R1 instruction, the control sequence involves:

  1. R3 and R1 are loaded into the appropriate registers.
  2. The control unit activates the ALU and selects the Multiply operation.
  3. The values from registers R3 and R1 are passed to the ALU via the data bus.
  4. The ALU performs the multiplication operation, and the result is stored back into register R3.

Q.8 What is Microinstruction? Explain Vertical and Horizontal organization of Microinstruction?

A microinstruction is a low-level instruction used in microprogramming, which is a technique for implementing the control unit of a CPU using microcode. Microinstructions typically control the operation of individual components within the CPU, such as registers, ALU, and data paths.

There are two main organizations of microinstructions: vertical and horizontal.

Vertical Organization:

In vertical organization, each microinstruction corresponds to a single control signal or operation within the CPU. Microinstructions are stored in vertical format, with each bit representing a control signal or operation. Vertical microinstructions are compact and efficient but may require a larger number of bits to encode complex operations.

Horizontal Organization:

In horizontal organization, each microinstruction represents a complete set of control signals for one or more operations within the CPU. Microinstructions are stored in horizontal format, with each bit representing a control signal for a specific operation. Horizontal microinstructions are more expressive and can encode complex operations more efficiently than vertical microinstructions.

Q.9 What is the difference between horizontal and vertical microinstruction?

The main difference between horizontal and vertical microinstructions lies in their organization and representation of control signals:

  • Vertical microinstructions represent each control signal or operation in a separate microinstruction bit, resulting in a tall, narrow format.
  • Horizontal microinstructions represent a complete set of control signals for one or more operations in a single microinstruction, resulting in a wide, flat format.

Horizontal microinstructions are more expressive and efficient for encoding complex operations, while vertical microinstructions are more compact but may require more bits to represent the same operations.

Q.11 Explain timing diagram of Read Operation.

The timing diagram of a read operation illustrates the sequence of events that occur when reading data from memory. Here's a typical timing diagram for a read operation:

[INSERT TIMING DIAGRAM HERE]

1. Address Setup: The address of the memory location to be read is placed on the address bus. 2. Address Strobe (AS): The AS signal is asserted to indicate that a valid address is present on the address bus. 3. Memory Access Time (tACC): The memory accesses the specified location and outputs the data onto the data bus. 4. Data Valid (DV): The DV signal indicates that the data on the data bus is valid and can be read by the CPU. 5. Data Setup Time (tDS): The CPU latches the data from the data bus. 6. Data Hold Time (tDH): The data remains stable on the data bus for a specified hold time after the DV signal is asserted.

Q.12 Explain how Word is fetched from a Memory?

Fetching a word from memory involves several steps:

  1. The CPU places the address of the desired memory location on the address bus.
  2. The CPU asserts the Read signal to indicate a read operation.
  3. The memory retrieves the data from the specified location and places it on the data bus.
  4. The CPU latches the data from the data bus into its internal registers.
  5. The CPU processes the fetched word according to the instruction being executed.

Q.13 Explain Microprogram Sequencing?

Microprogram sequencing refers to the process of determining the sequence of microinstructions to be executed to perform a particular instruction. It involves fetching and executing microinstructions from the microprogram control store based on the current state of the CPU and the instruction being executed.

Microprogram sequencing typically involves a finite state machine (FSM) that maintains the current state of the CPU and transitions between states based on the control signals and inputs. The FSM reads the next microinstruction address from the microprogram control store and updates the program counter accordingly to fetch the next microinstruction.

Q.14 What is datapath? Explain with the help of Labelled diagram.

The datapath is the part of the CPU responsible for executing instructions by performing arithmetic and logical operations on data. It consists of registers, arithmetic and logic units (ALU), and data paths that connect these components. Here's a labelled diagram illustrating the datapath:

[INSERT LABELLED DIAGRAM OF DATAPATH HERE]

The datapath receives instructions and operands from memory, processes them using the ALU, and stores the results back into registers or memory. Control signals generated by the control unit coordinate the operation of the datapath components to execute instructions.

Q.15 Draw the Single bus organization of the data Path of the CPU and show the control sequence for the Execution of MUL(R3), R1 for this organization?

[INSERT DIAGRAM OF SINGLE BUS ORGANIZATION HERE]

For the execution of MUL(R3), R1 in a single bus organization, the control sequence involves:

  1. Load R3 and R1 into the appropriate registers.
  2. Activate the ALU and select the Multiply operation.
  3. Pass the values from registers R3 and R1 to the ALU via the data bus.
  4. Perform the multiplication operation.
  5. Store the result back into register R3.

Fundamental Concepts of Processing Unit

1. Execution of a Complete Instruction

Execution of a computer instruction involves several steps in the processing unit:

  1. Instruction Fetch (IF): The CPU fetches the instruction from memory using the program counter (PC). The PC holds the address of the next instruction to be executed.
  2. Instruction Decode (ID): The fetched instruction is decoded to determine the operation to be performed and the operands involved. The instruction decoder generates control signals based on the opcode of the instruction.
  3. Operand Fetch (OF): If the instruction requires operands from memory, the CPU fetches them using their addresses provided by the instruction. Otherwise, operands may be fetched from registers.
  4. Execution (EX): The CPU performs the specified operation on the operands. This could involve arithmetic or logical operations, data transfers, or control flow operations.
  5. Result Writeback (WB): The result of the execution is written back to memory or registers, depending on the instruction. If the result is to be stored in memory, the CPU computes the memory address and writes the result.

2. Hardwired Control

Hardwired control is a control mechanism where the control signals required for instruction execution are generated by combinational logic circuits. These circuits are designed to produce the necessary control signals based on the opcode of the instruction and the current state of the CPU.

Hardwired control is fast and efficient but lacks flexibility. Once the control logic is implemented, it cannot be easily modified or updated without physically changing the circuitry.

3. Performance Consideration

Performance considerations in the processing unit play a crucial role in determining the efficiency of instruction execution:

  • Execution Time: The time taken to execute an instruction or a program. It depends on factors such as instruction complexity, clock frequency, and memory access time.
  • Throughput: The number of instructions processed per unit time. Higher throughput indicates better performance.
  • Latency: The delay between initiating a request and receiving a response. It includes memory access latency, instruction fetch latency, and processing latency.
  • Resource Utilization: Efficient use of hardware resources, such as registers, ALU, and memory. Maximizing resource utilization improves performance and reduces wastage of resources.

4. Microprogrammed Control

Microprogrammed control is an alternative to hardwired control where the control logic is stored in a control memory as microinstructions. Each microinstruction specifies a set of microoperations to be performed by the CPU.

Microprogrammed control provides greater flexibility as microinstructions can be easily modified or updated without changing the hardware. It also allows for more complex instruction sets and easier implementation of complex instructions.

5. Microinstructions

Microinstructions are low-level instructions that control the operation of the CPU at a microarchitectural level. Each microinstruction specifies a sequence of microoperations to be executed by the CPU.

Microoperations include reading from or writing to registers, performing arithmetic or logical operations, transferring data between registers and memory, and controlling the execution flow of instructions.

6. Microprogram Sequencing

Microprogram sequencing determines the order in which microinstructions are executed to carry out a complex instruction. It involves fetching microinstructions from the control memory and executing them sequentially, possibly branching or looping based on control signals.

Microprogram sequencing allows for the implementation of complex instruction sets by breaking down instructions into simpler microoperations and sequencing them appropriately.