UNIT-5
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1) Explain how enter a processing mechanism of 8086
works.explain interrupt types?
Interrupt mechanism:-
-The dictionary meaning of the
word interrupt is to break the sequence of operation. While the CPU is
executing the program, an interrupt breaks the normal sequence of execution of
instructions diverts its execution to some other program called interrupt service
routine(ISR). After executive ISR, the control is transferred back to main
program which was being executed at the time of interruption.
-Interrupt is the method of creating a temporary halt
during program execution and allows peripheral devices to access the
microprocessor. The microprocessor responds to that interrupt with an ISR
(Interrupt Service Routine), which is a short program to instruct the
microprocessor on how to handle the interrupt.
Hardware Interrupts
-Hardware interrupt is caused by any peripheral device by
sending a signal through a specified pin to the microprocessor.
-The 8086 has two hardware interrupt pins, i.e. NMI and
INTR. NMI is a nonmaskable interrupt and INTR is a maskable interrupt having
lower priority. One more interrupt pin associated is INTA called interrupt
acknowledge.
NMI
-It is a single non-maskable interrupt pin (NMI) having
higher priority than the maskable interrupt request pin (INTR)and it is of type
2 interrupt.The NMI is open used for parity errors and other major system for
such as power failure.
INTR
-The INTR is a maskable interrupt because the
microprocessor will be interrupted only if interrupts are enabled using set
interrupt flag instruction. It should not be enabled using clear interrupt Flag
instruction i.e INTR can be masked.
Software Interrupts
-Software interrupts are generated by some instruction used
in program. Basically software interrupt is generated by INT instruction.
Software interrupts are basically used for to allow the user to read the
keyboard, write text to screen, control disk drive, control printer, control
speaker and so forth. Some other software interrupts are INTO etc.
INT
- Interrupt instruction with type number.It is 2-byte
instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt are available.
2)Explain priority of interrupt with example?
Interrupts priority
-hardware, software, and internal interrupts are serviced
on a priority basis. Priority is achieved into ways. First, the interrupt
processing sequence implemented in the 8086 tests for the occurrence of the
various groups based on the hierarchy shown in table.Thus, we see that internal
interrupts are the highest-priority group, and external hardware interrupts are
the lowest- priority group. Second, each of the interrupts is given a different
priority level by assigning it a type number. Type 0 identify the highest
priority interrupt, and type 225 identifies the lowest- priority interrupt.
|
Interrupt |
Priority |
|
Reset |
Highest |
|
Internal
interrupts |
|
|
Software
interrupts |
|
|
NMI |
|
|
External
hardware interrupts |
Lowest |
-Actually,a few of the type numbers are not available for
use with software or hardware interrupts. This is because they are reserved for
special interrupt function of the 8086, such as internal interrupts. For
instance, within the internal interrupt group, the interrupt known as divide
error is a sign to type number 0. therefore it has the highest priority of the
internal interrupts. Another internal interrupt called overflow is a signed the
type number 4. Overflow is the lowest priority internal interrupt.
-The importance of interrupt lies in the fact that, even
interrupt-service routine has been initiated to perform a function a sign to a
specific priority level, only devices with higher priority are allowed to
interrupt the active service routine. Lower priority devices will have to wait
until the current routine is completed before their request for service can be
acknowledged. For hardware interrupts this priority scheme is implemented in
external hardware. For this reason, the user normally assigns task that must
not be interrupted frequently to higher-priority levels and those that can be
interrupted a lower-priority levels.
-A More common occurrence of multiple interrupt is seen
when the processor's trap flag is set. The trap flag, when set, puts the
processor into single-step mode, where a type-1 interrupt is generated after
completion of every instruction. If the current instruction is INT or INTO, you
can see that two interrupts will need servicing: INT or INTO interrupt and
single-step interrupt. Single- step has the lowest priority of all interrupts
and those gets recognized last.
3)Explain in detail the interrupt vector table(IVT) of 8086?
Interrupt Vector Table
Following figure shows the organization of IVT and
associated vector assignment.
-All types of interrupts whether hardware or software
generated points to the single entry in the processor interrupt vector table.
The interrupt vector table is located in the first 1024 bytes of the memory and
address 00000H to 003FFH. It contains 256 different 4 byte interrupt vectors.
-An interrupt vector contains the address of the interrupt service routines(ISR) of that interrupt. These table is a collection of 4 byte addresses that indicates where the processor should jump to execute the associated interrupt service routine. Because 256 types of inter types supported in real mode the IVT is 1024 bytes its long.This 1KB memory block is reserved for the table is located in the address range 00000H to 003FFH.
4)Explain operation of interrupt instructions?
1. CLI(Clear Interrupt Flag):-
-This instruction clears the interrupt flag.
2. STI(Set Interrupt Flag):-
-Instruction sets the interrupt flag.
3. WAIT (Wait for test signal or interrupt signal):-
-When this instruction executes the 8086 enters and idol condition in which it is
doing no processing.The 8086 will stay in this idle state until the 8086TEST input pin is made low or until an interrupt signal is received on the INTR or the NMl interrupt input pins. If a valid interrupt occurs while the 8086 is in this idle state the 8086 will return to the idle state after the interrupt service procedure executes. It returns to the idle state because the address of the WAIT instruction is the address pushed on the stack when the 8086 respond to the interrupt request. WAIT effects no flags. The WAIT instruction is used to synchronize the 8086 with external hardware such as the 8087 maths cooperation.
4. HLT (Halt until Interrupt or Reset):-
-The HLT instruction will cause the 8086 to stop fetching and executing instruction. The 8086 will enter a halt state. The only ways to get the processor out of the heart state are with an interrupt signal on the INTR pin, an interrupt signal on the NMI pin, or a reset signal on the RESET input.
5. INT n:-
-The INT n instruction calls the interrupt service routine
that begins at the address represented in vector number n. for example an INT
80H
So 00200H call the interrupt service routine whose address
is store in vector type number 00200H-00203H.
6. INTO (Interrupt Overflow):-
-The INTO instruction checks the overflow flag. If 0F = 1,
the INTO instruction cause the procedure whose address is stored in IVT in
vector type-4. If 0F = 0 the INTO instruction performs no operation and the
next sequential instruction in the program executed.
7. IRET (Interrupt Return):-
-The IRET instruction is a special return instruction used
to return for both software and hardware interrupts. The IRET instruction is
much like a normal FAR RET, because it retrieves the address from the stack. An
IRET instruction removes six bytes from the stack: two for IP, two for the CS,
and two for the flags.
5) Draw and explain the external hardware interrupt interface signals in minimum mode interrupt interface?
Minimum- Mode Interrupt Interface
The interrupt interface for 8086 system is shown in below
figure.
-Here we see that it includes the multiplexed address/data
bus and dedicated interrupt signal lines INTR and INTA. We also see that
external circuitry is required to interface the interrupt inputs, INT32 through
INT 255, to the 8086's interrupt interface.This interface circuitry must
identify which of the pending activity interrupts has the highest priority and
then pass its type number to the microprocessor.
-In this circuit we see that the key interrupt interface
signals are the interrupt request and interrupt acknowledgement. The input at
the INTR line signals the 8086 that and external device is requesting service.
The 8086 samples this input during the last clock period of each instruction
execution cycle. Logic 1 represents and active interrupt request.INTR is level
triggered therefore eats active 1level must be maintained until tested by the
8086.
-If it is not maintain the request for service may not be
recognized moreover the logic 1 at I NTR must be removed before the service
router runs to completion otherwise the same inter of make it acknowledged a
second time.
-When an interrupt request has been recognized by the 8086
its signals this fact to external circuitry. It does this with false to logic 0
at its interrupt acknowledgement output. Actually there are two pulses produced
at interrupt acknowledgement during the interrupt acknowledgement bus cycle.
The first poles signals external circuitry that the interrupt request has been
acknowledged and to prepare to send its type number to the 8086. The second
poles tales the external circuitry to put the type number on the data bus.
-Figure shows the maximum mod interrupt interface of the
8086 microprocessor. The primary difference between this interrupt interface
and that for the minimum mode is that the 8288 bus bus controller has been
added.In the minimum more system it is the bus controller that produces the
interrupt acknowledgement and ALE signals. Whenever the 8086 outputs and
interrupt acknowledgement bus status code the 8288 generates pulses at it's
interrupt acknowledgement output to signal external circuitry that the 8086 has
acknowledged an interrupt request.
-Second change in figure is that 8086 provides a new signal
for the interrupt interface. These output labeled block is called the bus
priority LOCK signal. LOCK is applied as an input to a bus arbiter. In response
to this signal the arbitration logic insurance that no other device can take over
control of the system bus until the interrupt acknowledge the cycle is
complete.
8) Explain with the help of a flowchart interrupt processing sequence of the 8086 microprocessor?
-Whenever interrupt is encounter processor follow some
steps to process the interrupt. That interrupt processing sequence can be
classified into following steps.
1. Get
vector number: first step is to obtain interrupt number there are three
possible ways for getting this number are:
•
The interrupt number maybe specified directly
one of the INT instruction, like INT 21H gives the interrupt number 21H.
•
The processor may automatically generated the
number, as it does for INTO, NMI, and divided error.
•
It may have to read the interrupt number from
the databus, after receiving INTR.
Once the interrupt number is obtained this number is used
to locate a location in the IVT by multiplying the number with 4. then IVT
gives address of ISR.
2. Save Processor Information:
Once the interrupt vector is known processor perform
some steps to save current information.
•
Processor pushes the flag register contains on
to the stack.
•
Processor clears the IF and TF this is important
for nested interrupt. If another interrupt encounters while processing first
then these flags will set again.
•
Processor the contents of CS register and IP
register. This is a return address. After interve processing control will
return to the address.
3. Fetch new instruction pointer:
what's the return address has been used processor can
fetch the new value of IP and CS out of the IVT and begin execution of the ISR.
4. Return from ISR:
Once interrupt service is over, the last instruction of the ISR which is IRET,
return the pointer to main program. IRET is similar of RET instruction of
procedure. RET instruction POPs return address out of stack, while IRET
instruction POPs return address as well as flag contents too. As RET is the
last Statement of the procedure similar IRET is the last Statement of the ISR.
9) Explain internal interrupt functions of 8086?
Internal Interrupt Functions 1.
Divide-Error(Type-0 or INT 0)
Whenever in division instructions denominators become zero
this interrupt generates.for example
Mov BL,0
DIV BL
These two lines code will generate type-0
interrupt.Processor will found ISR address from IVT and after execution of ISR
control will transfer to the next instruction.
2. Single-Step (type-1 or INT-1)
This interrupt relies on the setting of the trace flag in
the flag register. When the trace flag is said the 8086 will generate a type 1
interrupt after each instruction executes. This single step debugger maybe
perform to display the contents of each processor register, the state of the
flag, and other useful information after execution of each instruction in the
user program. Assume that the trace flag is set and trace ISR are display the
contents of AX register then following code will display the contents of AX
register after each step.
Mov AX, 1234H ; Display the contents of the AX=1234H
INC AL ; Display the contents of AX=1235H
DEC AH ; Display the contents of AX= 1135H
NOT AX ; Display the contents of AX=EECAH
Whenever this interrupt encounters processor generate a
type-1 interrupt and address of single step ISR is found from the address is
stored in memory locations 00004H through 00007H.
3. NMI (type-2 or INT-2)
-The non maskable interrupt is another interrupt
that is initiated from external hardware. However it differs from the other
external hardware interrupts in several ways. First as its name implies it
cannot be masked out with the interrupt flag. Second request for service by
this interrupt are signaled to the 8086 microprocessor by applying logic 1at
the NMI input, not the INTR input. Third, the NMI input is positive edge
triggered. Therefore, a request for service is automatically latched internal
to the MPU.
-Because NMI can never be ignored by the processor, it
finds useful application. One of them data saving on power fails. We know
processor unfortunately forgets the contents of its registers and flags when
power is turned off and thus has no chance of getting back to the correct place
in a program if its power is interrupted. One way to prevent these from
happening and provide a way for the processor to resume execution is to use NMI
to interrupt at the beginning of power failure. Because computers power supply
will continue to supply a stable voltage for a few microseconds after it loses
AC, the processor has plenty of time to execute the necessary instructions.
Suppose that a certain system contains a small amount of non volatile memory.
So in the event of power fail the NMI ISR should store the content of each
processor register in the NVM. These values can then be reloaded when power
comes backup.In this fashion we can recover from a power fail without loose of
intelligence.
-Whenever this interrupt occurs processor generate type 2
interrupt and fetches the ISR address from the memory location 00008H through
0000BH.
4.Breakpoint (type-3 or INT-3)
These interrupt is used for debugging purpose in the
programming. The working of these interrupt is as follows. A program being
debugged will have the first byte of one of its instructions replaced by the
code for breakpoint.
When the processor gets to this instruction it will
generate a type 3 interrupt.The ISR associated with break point is similar to
the trace ISR and should be capable of displaying the contents of processor
register and also the address at which the breakpoint byte with the original
first byte of the instruction.
When ever this interrupt occurs processor generated type-3
interrupt and fetches the ISR address from the memory location 0000CH through
0000FH.
5. Overflow (type-4 or INT-4)
This type-4 interrupt is initiated only when the INTO
instruction is executed with the overflow flag is set.If the overflow flag is
cleared, INTO will not generate an interrupt.
For example:
Mov AL, 70H
Mov BL, 60H
ADD AL, BL
INTO
These series of instructions will generate an overflow
interrupt.when ever this interrupt occurs processor generates type-4 interrupt
and fetches the ISR address from the memory location 00010H through 00013H.
10) Differentiate
between Procedure call and ISR call?
|
Procedure call |
ISR call |
|
Procedure
is called by CALL statement |
ISR
may be called by interrupt type or it may be hardware generated. |
|
In procedure call only
return address is pushed into the stack,this address may be one word long. |
ISR
call processor is always called directly while ISR is always called
indirectly through IVT |
|
Procedure
is always called directly |
ISR is always called
indirectly through IVT |
|
Last
statement of procedure is RET |
Last
statement of ISR is IRET |
11) What
are the different ways interrupts are generated?
-There are two types of interrupts: software interrupts and
hardware interrupts. Software interrupts are generated by the software
instructions like INT and interrupt number.
For example: INT 21H will generate interrupt of type 21H.
INTO will generate overflow interrupt. BOUND generates a type-5 interrupt.
Hardware interrupts are generated by hardware pins. As NMI and INTR pins are
available to generate these interrupts. One extra pin INTA gives interrupt
acknowledgement.
12)What is the IVT address for the INT 21H?
-As 21 hexadecimal is equivalent to 33 decimal so multiply
this number by 4.
33 * 4 = 132 decimal =(84)16, so the IP address will be
stored at address 00084H and 00085H and CS value will be store at 00086H and
00087H memory location.
Initial IVT address will be 00084H.
13) Write an interrupt service routine that will multiply the contents of AX by 7.If the new value of AX is greater than 8400H, call the far routine OVERSAN. Note OVERSCAN destroys AX, BX, and DI.
Solution:-
PUSH BX
PUSH DI
Mov BL,7
IMUL BL
CMP AX, 8400H
JLE EXIT
PUSH AX
CALL FAR PTR OVERSCAN
POP AX
EXIT: POP DI
POP BX
IRET
14) Show the map of IVT, Stack if an instruction INT 21H is executed, assuming that following values: SS=1000H, SP=0200H, CS= 2000H, IP=1234H. Flags=3456H; address of ISR 21 IS 3000H:5678H.
Solution:- To
map IVT and Stack we have to calculate some addresses.
1.Stack top address SS * 10 + SP = 10000H + 0200H = 10200H.
2.IVT address for INT 21H is 00084H and 00085H for IP and
00086H and 00087H for CS.
Now follow interrupt processing sequence.
1.Process encounters INT 21H interrupt.
2.Processor pushes the contents of flag register onto the
stack.
3.Processor pushes the contents return address CS:IP onto
the stack.
4.Processor fetches the new address of ISR from IVT.
