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Q1) Draw the block diagram of 8086 architecture.
Functional Block Diagram of 8086 Microprocessor
The 8086 is a 16-bit microprocessor.
The term 16 bit implies that its arithmetic logic unit, its internal registers, and most of its instructions are intended to work with 16 bit binary data.
The 8086 has a 16 bit data bus, so it can read data from or write data to memory and ports either 16 bits or 8 bits at a time.
The 8086 has a 20 bit address bus, so it can address any one of 220, or 1,048,576 memory locations.
8086 CPU is divided into 2 independent functional parts to speed up the processing namely BIU (Bus interface unit) & EU (execution unit).
Q2) Explain register organization of 8086.
Register organization of 8086
The registers AX, BX, CX, and DX are the general 16-bit registers.
AX Register: Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte.
BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment. It is used as offset storage for forming physical address in case of certain addressing mode.
CX Register: It is used as default counter or count register in case of string and loop instructions.
DX Register: Data register can be used as a port number in I/O operations and implicit operand or destination in case of few instructions. In integer 32-bit multiply and divide
instruction the DX register contains high-order word of the initial or resulting number.
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored.
DS register can be changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data.
Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.
Conditional flags are as follows:
Carry Flag (CY): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic.
Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e.carry given by D3 bit to D4 is AC flag. This is not a general-purpose flag, it is used internally by the Processor to perform Binary to BCD conversion.
Control flags are set or reset deliberately to control the operations of the execution unit.
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Segmentation is the process in which the main memory of the computer is divided into different segments and each segment has its own base address. It is basically used to enhance the speed of execution of the computer system, so that processor is able to fetch and execute the data from the memory easily and fast. Need for Segmentation – The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as Segment Registers. Code segment register (CS): is
used for addressing memory location in the code segment of the
memory, where the executable program is stored. Data segment register (DS): points
to the data segment of the memory where the data is stored. Extra Segment Register (ES): also refers to a
segment in the memory which is another data segment in the memory. Stack Segment Register (SS): is used for
addressing stack segment of the memory. The stack
segment is that segment of memory which is used to store stack
data. The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the 1MB memory locations. The four segment registers actually contain the upper 16 bits of the starting addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of time. A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up of contiguous memory locations. It is independent, separately addressable unit. Starting address will always be changing. It will not be fixed. Note that the 8086 does not work the whole 1MB memory at any given time. However it works only with four 64KB segments within the whole 1MB memory. Bellow is the one way of positioning four 64 kilobyte segments within the 1M byte memory space of an 8086. |
Types Of Segmentation –
1. Overlapping Segment – A segment starts at a particular address and its maximum size can go up to 64kilobytes. But if another segment starts along this 64kilobytes location of the first segment, then the two are said to be Overlapping Segment.
Advantages of the
Segmentation The main advantages of segmentation are as follows:
●It provides a powerful memory management mechanism.
●Data related or stack related operations can be performed in different segments.
● Code related
operation can be done in separate code segments.
● It allows to
processes to easily share data.
● It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16 bit registers to give an addressing capability of 1 Megabytes. Without segmentation, it would require 20 bit registers.
● It is possible to enhance the memory size of code data or stack segments beyond 64 KB by allotting more than one segment for each area.
Q4) Explain physical address generation in 8086.
Physical
Address Formation
The 80386 provides a one Mbyte + 64 Kbyte memory
space for an 8086 program. Segment relocation is performed as in the 8086: the
16-bit value in a segment selector is shifted left by four bits to form the
base address of a segment. The effective address is extended with four high
order zeros and added to the base to form a linear address as Figure 14-1 illustrates. (The linear address is equivalent to the physical address,
because paging is not used in real-address mode.) Unlike the 8086, the
resulting linear address may have up to 21 significant bits. There is a
possibility of a carry when the base address is added to the effective address.
On the 8086, the carried bit is truncated, whereas on the 80386 the carried bit
is stored in bit position 20 of the linear address.
Unlike the 8086 and 80286, 32-bit effective
addresses can be generated (via the address-size prefix); however, the value of
a 32-bit address may not exceed 65535 without causing an exception. For full
compatibility with 80286 real-address mode, pseudo-protection faults (interrupt
12 or 13 with no error code) occur if an effective address is generated outside
the range 0 through 65535.
Q5) Explain 16 bit 8086 flag register.
Flag register of 8086 microprocessor
The Flag register is a Special Purpose Register. Depending upon the value of result after any arithmetic and logical operation the flag bits become set (1) or reset (0).
Figure – Format of flag register
There are total 9 flags in 8086 and the flag register is
divided into two types:
(a) Status Flags – There are 6 flag registers in 8086 microprocessor which become set(1) or reset(0) depending upon condition after either 8-bit or 16-bit operation. These flags are conditional/status flags. 5 of these flags are same as in case of 8085 microprocessor and their working is also same as in 8085 microprocessor. The sixth one is the overflow flag. The 6 status flags are:
2. Parity Flag (P)
3. Carry Flag (CY)
These first five
flags are defined here
Overflow Flag (O) – This flag will be set (1) if the result
of a signed operation is too large to fit in the number of bits available to
represent it, otherwise reset (0). After any operation, if D[6] generates any
carry and passes to D[7] OR if D[6] does not generates carry but D[7] genSign
Flag (S)
4. Zero Flag (Z)
Auxiliary Cary Flag (Aerates, overflow flag becomes set,
i.e., 1. If D[6] and D[7] both generate carry or both do not generate any
carry, then overflow flag becomes reset, i.e., 0.
Example: On adding bytes 100 + 50 (result is not in range
-128…127), so overflow flag will set.
MOV BL, 32 (32 is 00110010 which is positive)
ADD AL, BL (82 is 10000010 which is negative)
5. Overflow flag became set as we added 2 +ve numbers and we got a -ve number.
(b) Control Flags – The control flags enable or disable certain operations of the microprocessor. There are 3 control flags in 8086 microprocessor and these are:
1.Directional Flag (D) – This flag is specifically used in string instructions.
If directional flag is set (1), then access the string data from higher memory location towards lower memory location.
If directional flag is reset (0), then access the string data from lower memory location towards higher memory location.
2.Interrupt Flag (I) – This flag is for interrupts.
If interrupt flag is set (1), the microprocessor will recognize interrupt requests from the peripherals.
If interrupt flag is reset (0), the microprocessor will not recognize any interrupt requests and will ignore them.
3.Trap Flag (T) – This flag is used for on-chip debugging. Setting trap flag puts the microprocessor into single step mode for debugging. In single stepping, the microprocessor executes a instruction and enters into single step ISR.
If trap flag is set (1), the CPU automatically generates an internal interrupt after each instruction, allowing a program to be inspected as it executes instruction by instruction.
If trap flag is reset (0), no function is performed.
a) INTR
INTR : Interrupt Request. This is triggered input. This is
sampled during the last clock cycles of each instruction for determining the
availability of the request. If any interrupt request is found pending, the
processor enters the interrupt acknowledge cycle. This can be internally masked
after resulting the interrupt enable flag. This signal is active high(1) and
has been synchronized internally.
MN/MX’ : Minimum/Maximum. This pin signal indicates what
mode the processor will operate in.
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST
pin goes low(0), execution will continue, else the processor remains in an idle
state. The input is internally synchronized during each of the clock cycle on
leading edge of the clock.
LOCK’ : Its an active low pin. It indicates that other
system bus masters have not been allowed to gain control of the system bus
while LOCK’ is active low(0). The LOCK signal will be active until the
completion of the next instruction
ALE : Address Latch Enable. ALE is provided by the
microprocessor to latch the address into the 8282 or 8283 address latch. It is
an active high(1) pulse during T1 of any bus cycle. ALE signal is never
floated, is always integer.
BHE’/S7 : Bus High Enable/Status. During T1 it is low. It is
used to enable data onto the most significant half of data bus, D8-D15. 8-bit
device connected to upper half of the data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7. S7 signal is available during T2, T3 and
T4.
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 nstruction queue according to the table shown below
1 0
0 0 No operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
want to use an 8286 or 8287 data bus transceiver. The direction of data flow is
controlled through the transceiver.
Q7)Explain the concept of Instruction queue.
The Instruction Queue:
The execution
unit (EU) is supposed to decode or execute an instruction. When EU is busy in
decoding and executing an instruction, the BIU fetches up to six instruction bytes for the next instructions.
These bytes are called as the pre-fetched
bytes and they are stored in a first in first out (FIFO) register set,
which is called as a queue.
The fetching
of opcodes well in advance, prior to their need for execution increases the
overall efficiency of the processor boosting its speed. The processor no longer
has to wait for the memory access operations for the subsequent instruction
opcode to complete.
Instruction queue is 6 bytes so that it can store the longest instruction. 8086 is the Ist processor to support Instruction Queue.
Q8)Explain 8086 addressing modes for sequential
instruction.
Q9)Explain addressing modes for control transfer
instruction.
Q10) Explain following 8086 instruction
MOV: Moves data from register to register, register to memory, memory to register, memory to accumulator, accumulator to memory, etc.
XCHG: Exchanges the contents of the 16-bit or 8-bit specified register with the contents of AX register, specified register or memory locations.
LDS: Loads a word from the specified memory locations into specified register. It also loads a word from the next two memory locations into DS register.
LES: Loads a word from the specified memory locations into the specified register. It also loads a word from next two memory locations into ES register.
XCHG: Exchanges the contents of the 16-bit or 8-bit specified register with the contents of AX register, specified register or memory locations.
IN: Transfers data from a port to the accumulator or AX, DX or AL register
XOR: Performs bit by bit logical XOR operation of two operands and places the result in the specified destination.
SHR: Shift each bit of operand right by specified number of bits and put zero in MSB position.
ROR: Rotate all bits of the operand right by specified number of bits.
Q11)Explain flag manipulation and process
control instruction.
Flag Manipulation and Processor
Control Instructions
Instructions of this instruction set are
related to flag manipulation and machine control.
The following instructions come under
this category:
Instructs Description |
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CLC |
Clear Carry
Flag: This instruction resets the carry flag CF to 0. |
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CLD |
Clear
Direction Flag: This instruction resets the direction flag DF to 0. |
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CLI |
Clear
Interrupt Flag: This instruction resets the interrupt flag IF to 0. |
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CMC |
This instruction take complement of
carry flag CF. |
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STC |
Set carry flag CF to 1. |
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STD |
Set direction flag to 1. |
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STI |
Set interrupt flag IF to 1. |
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HLT |
Halt processing. It stops program
execution. |
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NOP |
Performs no operation. |
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ESC |
Escape: makes bus
free for external master like a coprocessor or peripheral device. |
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WAIT |
When WAIT instruction is executed,
the processor enters an idle state in which the processor does no processing. |
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LOCK |
It is a prefix instruction. It makes
the LOCK pin low till the execution of the next instruction. |
